Implementation of LVDS Differential High Speed ​​Transmission in Xilinx FPGA

Low-voltage differential transmission technology is based on low-voltage differential signaling (Low Volt-agc DifferenTIal signaling) transmission technology. High-speed signal transmission from one board system to fast data transmission between different circuit systems can be implemented by low-voltage differential transmission technology. Its application is becoming more and more important. Low-voltage differential signals have higher noise rejection than single-ended transmissions, and their lower voltage swing allows differential pairing to have higher data rates, consume less power, and produce lower electromagnetic emissions.

LVDS: Low Voltage DifferenTIal Signaling, low voltage differential signal.
LVDS transmission support rates are typically above 155 Mbps (approximately 77 MHz).
LVDS is a low-swing differential signaling technology that allows signals to be transmitted at hundreds of Mbps over differential PCB pairs or balanced cables. Low-voltage and low-current drive outputs achieve low noise and low power.

Differential signal noise immunity

As can be seen from the differential signal transmission line, if the ideal condition, the line does not interfere,
On the sending side, it can be understood as:
IN= IN+ — IN-
On the receiving side, it can be understood as:
IN+ — IN- =OUT
and so:
OUT = IN
In the actual line transmission, the line has interference and appears on the differential pair at the same time.
On the sending side, it is still:
IN = IN+ — IN-
The line transmission interference exists on the differential pair at the same time. If the interference is q, the reception is:
(IN+ + q) — (IN- + q) = IN+ — IN- = OUT
and so:
OUT = IN

The noise is suppressed. The above can visually understand the ability of the differential method to suppress noise.

Use of Xilinx's differential primitives

(The original language, whose English name is PrimiTIve, is the name of a series of commonly used modules developed by Xilinx for its device features. Users can think of it as a library function provided by Xilinx for users, similar to the key such as "cout" in C++. The word is the basic component in the chip, which represents the hardware logic unit actually owned by the FPGA, such as LUT, D flip-flop, RAM, etc., which is equivalent to the machine language in the software. When implementing the translation steps in the process, all the words The design unit is translated into the basic components in the target device, otherwise it is not implementable. The primitive can be directly instantiated in the design, is the most direct code input method, its relationship with the HDL language, similar to assembly language and C The relationship of language.)

Differential I/O port component

1) IBUFDS

The IBUFDS primitive is used to convert a differential input signal into a standard single-ended signal with optional delay added. In the IBUFDS primitive, the input signals are I, IB, one is dominant, and one is slave, and the two phases are opposite.
The logical truth table of IBUFDS is listed, where "-*" means that the output maintains the last output value and remains unchanged.

The instantiation code template for the IBUFDS primitive is as follows:

// IBUFDS: Differential input buffer (DifferenTIal Input Buffer)
// Applicable chip: Virtex-II/II-Pro/4, Spartan-3/3E
// Xilinx HDL Library Wizard version, ISE 9.1
IBUFDS #(
.DIFF_TERM("FALSE"),
// Differential terminal, only available on Virtex-4 series chips, can be set to True/Flase
.IOSTANDARD("DEFAULT")
/ / Specify the level standard of the input port, if not sure, can be set to DEFAULT
) IBUFDS_inst (
.O(O), // clock buffered output
.I(I), // The positive input of the differential clock needs to be directly connected to the port of the top module
.IB(IB) // Negative input of the differential clock, which needs to be directly connected to the port of the top module
);
// End the instantiation process of the IBUFDS module

2) OBUFDS

OBUFDS converts standard single-ended signals into differential signals. The output port needs to directly correspond to the output signal of the top-level module, and IBUFDS is a pair of reciprocal operations. The truth table for the OBUFDS primitives is listed in the table.

The instantiation code template for the OBUFDS primitive is as follows:

// OBUFDS: Differential Output Buffer
// Applicable chip: Virtex-II/II-Pro/4, Spartan-3/3E
// Xilinx HDL Library Wizard version, ISE 9.1
OBUFDS #(
.IOSTANDARD("DEFAULT")
// The level standard of the named output port
) OBUFDS_inst (
.O(O), // differential positive output, directly connected to the top module port
.OB(OB), // differential negative output, directly connected to the top module port
.I(I) // buffer input
);
// End the instantiation process of the OBUFDS module

3) IOBUFDS

Verilog Instantiation Template

// IOBUFDS: Differential Bi-directional Buffer

// Virtex-II/II-Pro/4/5, Spartan-3/3E/3A

// Xilinx HDL Libraries Guide, version 9.1i

IOBUFDS #(

.IBUF_DELAY_VALUE("0"),

// Specify the amount of added input delay for the buffer, "0"-"16" (Spartan-

3E only)

.IFD_DELAY_VALUE("AUTO"),

// Specify the amount of added delay for input register, "AUTO", "0"-"8"

(Spartan-3E only)

.IOSTANDARD("DEFAULT") // Specify the I/O standard

) IOBUFDS_inst (

.O(O), // Buffer output

.IO(IO), // Diff_p inout (connect directly to top-level port)

.IOB(IOB), // Diff_n inout (connect directly to top-level port)

.I(I), // Buffer input

.T(T) // 3-state enable input

);

// End of IOBUFDS_inst instantiation

Differential clock component

1) IBUFGDS

Primitives related to global clock resources commonly used in the global clock resources related to the Xilinx device primitives include: IBUFG, IBUFGDS, BUFG, BUFGP, BUFGCE, BUFGMUX, BUFGDLL and DCM, as shown in Figure 1.

IBUFGDS is a differential form of IBUFG. When a signal is input from a pair of differential global clock pins, IBUFGDS must be used as the global clock input buffer. IBUFG supports IO standards in various formats such as BLVDS, LDT, LVDSEXT, LVDS, LVPECL and ULVDS.

Verilog Instantiation Template

IBUFGDS instanece_name(.O(user_O),

.I (user_I),

.IB (user_IB));

Reference materials:

1) Research on high-speed communication application based on LVDS technology and FPGA, Han Dangqun, Tang Zhengbing, Zhang Qingling

2) Introduction to LVDS principle and application

3) National Semiconductor's LVDS User Manual

How Xilinx FPGAs Use LVDS

Regardless of whether you use HDL flow or schematic flow, you only need to instantiate IBUFDS, OBUFDS and other differential buffers, you can use LVDS.

After instantiation, to locate the Pin position, use PACE, select LVDS33 or LVDS25 in IO Standard, and choose the version with DCI. When setting the port, pay attention to see the name of the Pin in the Datasheet is P/N. This P also corresponds to the P in the buffer, and N also corresponds to N. And note that the same bank can only have one voltage standard.

If you use the FPGA Editor to observe the situation after the layout and routing, you will find that there is no IBUFDS component in the FPGA Editor. This Buffer is hidden in the IOB. Click on the Pin tile to see that there is a Buffer inside. I have the role of IBUFDS.

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