At present, many SOC manufacturers' microprocessor chips integrate LCD controllers, such as Samsung's S3C2410.S3C2440 and Intel's Xscale series. Most embedded systems also use popular LCD display technology. However, in the case where a large screen display is required and the resolution is not high, such as a workshop or a factory building, the use of a large screen LCD is costly. On the other hand, VGA display technology is still being used in large quantities because of its mature technology and low cost. Until today, it is still the most mature standard interface for all display terminals. If the embedded processor directly supports the VGA display, it can greatly utilize existing resources and save system cost.
1 Analysis of VGA display technology based on S3C2440
By analyzing the timing logic of the VGA display technology and the sequential logic of the S3C2440 integrated LCD controller to drive the TFT LCD, find out their commonalities and analyze the feasibility of applying the VGA display interface on the S3C2440.
1.1 VGA display principle
VGA (Video Graphics Arrnay) is a display interface that IBM is still widely used in PCs. The interface has the advantages of high resolution, fast display speed, rich colors, etc., and has been widely used in the field of color display. The VGA interface physically represents the DB15 socket, and the VGA adapter end uses the female DB15 standard interface. Its pin definition is shown in Table 1.
Table 1 VGA Adapter Pin Definitions
The VGA interface uses analog RGB channels for point-by-point, progressive scan. The timing is shown in Figure 1. The VGA interface signal is an analog signal, and there are five key signals, which are Horizontal Sync horizontal synchronization signal (also called horizontal synchronization signal), vertical synchronization signal VerTIcal Sync (also called field synchronization signal), red analog signal, green analog signal and Basket color analog signal. The electron gun scans from left to right and from top to bottom, and at the end of each line, the line sync signal is used for synchronization. Field sync is performed using the field sync signal after all lines have been scanned. Since the deflection of the electron gun takes time, it is necessary to perform blanking control on the electron gun after the sweep is completed, and blanking is performed during the rotation process after the end of each line, and the field blanking is performed during the rotation process after each end. The electron beam is not sent during the blanking process.
Figure 1 VGA scan timing
1. 2 TFT LCD display scan timing analysis
The S3C2440 chip based on the ARM920T core integrates an LCD controller. The LCD controller is used to transmit image data to the LCD and provide necessary control signals such as VFRAME, VLINE, VCLK, VM, etc. In addition, the LCD controller includes a set of control registers: LCDCON1 register, LCDCON2 register, LCDCON3 register, LCDCON4 register, LCD CON5 register. The setting of these registers is closely related to the display information, control timing and data transmission format. In the design, these registers need to be correctly set according to the specific information of the display device, so that the S3C2440 can control and drive different displays normally.
The scanning sequence of the TFT LCD screen is shown in Figure 2.
Figure 2 Typical TFT LCD scan timing
These mainly include:
1) Frame (Vertical) Synchronization (VSYNC): A high level (or low level) is used to indicate the start of scanning a frame.
2) Line (horizontal) synchronization (HSYNC): A high level (or low level) is used to indicate the start of a line scan.
3) Clock (VCLK): Write data to the LCD through the rising edge (or falling edge).
4) Data effective control (VDEN): Indicates whether to enable the TFT output.
5) Data signal (VD): indicates the color of each point, usually in 16-bit, 18-bit, 24-bit mode.
By comparing the timing of the VGA interface with the scanning timing of the TFT LCD screen, it can be seen that they are very similar. This provides an inherent possibility to drive the VGA display with an LCD controller. Moreover, once this switching scheme is implemented, it is the most convenient solution for extending the VGA interface on the embedded system platform because it is an electrical conversion of two interfaces implemented by hardware, without writing any driver. Comparing the characteristics of the two interfaces, to achieve the conversion from TFT timing to VGA timing, the problems that need to be solved are:
1) The level of the TFT liquid crystal scanning sync signal and the VGA sync signal.
2) The output of the TFT liquid crystal controller is the RGB digital interface, while the red, green and blue channels of the VGA are analog, and both need to be converted by D/A. When using D/A, consider the issues of conversion accuracy, conversion speed, and number of conversion channels. Among them, in order to meet the requirements of true color (24 bits), 8-bit conversion accuracy is sufficient. Based on the frame rate requirement of VGA, the conversion frequency of each point must be greater than 27 MHz. At the same time, at least 3 channels must be converted simultaneously to meet the output of 3 channels of red, green and blue (RGB).
The D/A for this conversion is usually called video D/A. This design uses ATI's video D/A chip ADV7120.
1.3 Introduction to ADV7120
The ADV7120 is a high-speed video digital-to-analog converter chip produced by Analog Devices, Inc., with a pixel scan clock frequency of three levels of 30, 50, and 80 MHz. The ADV7120 integrates three independent 8-bit high-speed D/A converters on a single chip to process red, green, and blue video data separately. It is especially suitable for display terminals with high-resolution analog interfaces and high-speed D/A conversion. operating system.
The input and control signals of ADV7120 are very simple: 3 groups of 8-bit digital video data input terminals respectively correspond to RGB video data, and the data input terminal adopts standard TTL level interface; 4 video control signal lines include composite sync signal SYNC, blanking Signal BLANK, white level reference signal REFWHITE and line clock signal CLOCK; external 1.23 V digital-to-analog conversion reference voltage source and 1 output full-scale adjustment. There are only 4 output signal lines: the analog RGB signal uses a high-impedance current source output mode, which can directly drive a 75 Î© coaxial transmission line; the synchronous reference current output signal Isync is used to encode video synchronization information in the green video analog signal.
2 VGA interface circuit design
As mentioned above, the timing of the VGA interface and the timing of the LCD scanning interface are the same. The block diagram of the conversion module of the TFT liquid crystal timing to the VGA interface composed of the ADV7120 is shown in FIG.
Figure 3 VGA interface circuit block diagram
According to the data sheet of the ADV7120, the ADV7120 has a high level of reference level and cannot be replaced by a resistor divider circuit. In this design, the 1.235 V voltage reference chip AD589 is used to generate the reference voltage.
3 VGA display mode selection and corresponding control register settings in the S3C2440 LCD controller
The original VGA display contains several modes. The initial VGA resolution is defined as 640x480. Then the higher resolution SVGA, XVGA and other standards are proposed based on this. The interface is compatible with the VGA standard, so it is customary to put all This type of interface is called a VGA interface. Different display modes have different time parameters in the VGA timing. After selecting a display mode, the LCD controller must be configured so that the timing parameters generated are in accordance with the VGA mode requirements, so that the VGA interface can be successfully driven, otherwise VGA The display will flash, blur, or even not display.
Here, a VGA display mode with a resolution of 640x480, a refresh rate of 60 Hz, and a 16-bit color is selected, and the configuration of the LCD controller related registers is completed in this mode. The timing logic output by the LCD controller can meet the requirements of the VGA display in this mode. The timing of the VGA interface sync signal in this mode is shown in Figure 4.
Figure 4 VGA interface synchronization signal timing
The control registers in the main LCD controller are configured according to the VGA interface sync signal timing of Figure 4:
1) LCDCON1 register
CLKVAL: A parameter that determines the VCLK frequency. The formula is VCLK-HCLK/[(CLKVAL+1)x2]. In this design, HCLK=100 MHz of S3C2440, the display needs VCLK=20MHz, so CLKVAL=1 should be set.
BPPMODE: Determine BPP (bit spread per pixel). Select BPPMODE=0xC to select TFT 16-bit mode.
2) LCDCON2 register
VBPD: Determines the delay before the frame synchronization signal and the frame data transmission, which is the ratio of the delay time before the frame data transmission and the width of the line synchronization clock interval. Referring to the time data in FIG. 4, VBPD=t3/t6=1.02 ms/31.77 Ss=32.
LINEVAL: Determines the vertical size of the display. Formula: LINEVAL=YSIZE-1=479.
VFPD: Determines a delay from the completion of the frame data transmission to the arrival of the next frame synchronization signal, which is the ratio of the delay time after the frame data transmission and the width of the line synchronization clock interval. Referring to the time data in FIG. 4, VFPD=t5/t6 =0.35 ms/31.77 Î¼s=11.
VSPW: Determines the frame sync clock pulse width, which is the ratio of the frame sync signal clock width to the line sync clock interval width. As shown in Figure 4, VSPW = t2 / t6 = 0.06 ms / 31.77 Î¼s = 2.
3) LCDCON3 register
HBPD: Determines the delay before the line sync signal and line data transmission, and describes the number of VCLK pulses in the delay time before the line data transmission, as shown in Figure 4, VBPD = t7xVCLK = 1.89 Î¼s x 25 MHz = 47.
HOZAL: Determines the horizontal dimension of the display. Here HOZAL=XSIZE-1=639.
HFPD: Determines the delay time from the completion of the line data transmission to the arrival of the next line of synchronization signals, and describes the number of VCLK pulses in the delay time after the line data transmission, as shown in Figure 4, HFPD = t9xVC LK = 0.94 Î¼s x 25 MHz = 24.
4) LCDCON4 register
HSPW: Determines the line sync clock pulse width. Describe the number of VCLK pulses in the line sync pulse width time, as shown in Figure 4, HSPW = 3.77 Î¼s x 25 MHz = 94.
5) LCDCON5 register
BPP24BL: Determine the data storage format. Set BPP24BL=0x0 here, that is, select the little end mode storage.
FRM565: Determine the 16-bit data output format. Set FRM565=0x1, that is, select the output format of 5:6:5.
By designing the VGA interface circuit and setting the LCD controller registers accordingly, the seamless connection between the LCD digital output and the D/A conversion is realized, and the image information originally outputted on the LCD can be obtained without any additional driver. Output to the VGA display.
4 Tests and conclusions
This design demonstrates the feasibility of using the S3C2440's own LCD controler to drive the VGA display by analyzing the timing of the VGA interface timing and the S3C2440TFT LCD interface timing. The timing matching is the most critical part of the design success, meeting the interface timing requirements. Under the premise, the high-speed three-way 8-bit video D/A chip converts the digital RGB signal of the LCD interface into the analog signal required by the VGA interface. The experiment proves that the image information passes through the VGA conversion circuit and displays well on the display screen without obvious jitter, which satisfies the ordinary display requirements. Because the host uses ARM embedded microprocessor, compared with the traditional X86 host, the cost of the whole system is greatly reduced. This inexpensive and simple display solution can be widely applied to various occasions where the display effect is not high but a large-sized screen is required.
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