Asynchronous reset, synchronous release mode, and the reset signal is active low

First, the characteristics:

Synchronous reset: As the name suggests, synchronous reset means that the reset signal is valid only when the rising edge of the clock arrives. Otherwise, the reset of the system cannot be completed. Described as Verilog as follows:
Always @ (posedge clk) begin
If (!Rst_n)
...
End
Asynchronous reset: It means that the system is reset as long as the clock edge is present, as long as the reset signal is valid. Described as Verilog as follows:
Always @ (posedge clk,negedge Rst_n) begin
If (!Rst_n)
...
End

Second, their respective advantages and disadvantages:

1. In general, there are about three advantages of synchronous reset:
a, is conducive to the simulation of the simulator.
b. The designed system can be made into a 100% synchronous sequential circuit, which greatly facilitates timing analysis, and the integrated fmax is generally higher.
c. Because it is valid only when the clock active level comes, it is possible to filter out glitches above the clock frequency.
There are also many shortcomings, mainly the following:
a. The effective duration of the reset signal must be greater than the clock period in order to be truly recognized by the system and complete the reset task. Also consider factors such as clk skew, combined logic path delay, reset delay, and so on.
b. Since most of the logic devices have only the asynchronous reset port in the DFF of the target library, if the synchronous reset is used, the synthesizer will insert the combination logic into the data input port of the register, which will consume more logic. Resources.
2, for asynchronous reset, his advantages are also three, are corresponding:
a. Most target device library dffs have asynchronous reset ports, so asynchronous reset can save resources.
b, the design is relatively simple.
c. Asynchronous reset signal identification is convenient, and the global reset port GSR of the FPGA can be conveniently used.
Disadvantages:
a. It is prone to problems when the reset signal is released. Specifically, if the reset is released just near the valid edge of the clock, it is easy to make the register output metastable, resulting in metastability.
b, the reset signal is susceptible to burrs.

Third, summary:

Therefore, it is generally recommended to use asynchronous reset, synchronous release mode, and the reset signal is active low. This will give you the best of both worlds.

Always @(posedge clk or negedge rst_n)

If(!rst_n) b <= 1'b0;

Else b <= a;

Asynchronous reset, synchronous release mode, and the reset signal is active low

We can see that the FPGA registers have an asynchronous clear (CLR). In the asynchronous reset design, this port is usually connected to the active low reset signal rst_n. Even if your design is a high-level reset, then the actual integration will reverse your reset signal to the CLR end.

An example of a simple asynchronous reset

Always @ (posedge clk or negedge rst_n)

If(!rst_n) b <= 1'b0;

Else b <= a;

Asynchronous reset, synchronous release mode, and the reset signal is active low

We can see that the FPGA registers have an asynchronous clear (CLR). In the asynchronous reset design, this port is usually connected to the active low reset signal rst_n. Even if your design is a high-level reset, then the actual integration will reverse your reset signal to the CLR end.

A simple example of synchronous reset

Always @ (posedge clk)

If(!rst_n) b <= 1'b0;

Else b <= a;

Asynchronous reset, synchronous release mode, and the reset signal is active low

Compared with the asynchronous reset, the synchronous reset does not use the CLR port of the upper register. The integrated actual circuit only uses the reset signal rst_n as the enable signal of the input logic. Then, such a synchronous reset is bound to increase the internal resource consumption of the FPGA.

So what about synchronous reset and asynchronous reset?

It can only be said that each has its own advantages and disadvantages. The good thing about synchronous reset is that it only triggers the judgment of whether the system is reset at the rising edge of the clock signal clk, which reduces the probability of occurrence of metastability; its bad is also said that it needs to consume more device resources. This is what we don't want to see. The registers of the FPGA have dedicated ports for asynchronous reset. The ports with asynchronous reset do not need to increase the consumption of device resources, but the asynchronous reset also has hidden dangers. The privileged classmates have never realized or seen them in the past. The metastable problem of the asynchronous clock domain also exists between the asynchronous reset signal and the system clock signal.

Look at the following example of a two-level register asynchronous reset

Always @ (posedge clk or negedge rst_n)

If(!rst_n) b <= 1'b0;

Else b <= a;

Asynchronous reset, synchronous release mode, and the reset signal is active low

Always @ (posedge clk or negedge rst_n)

If(!rst_n) c <= 1'b0;

Else c <= b;

In this way, the problem of resource consumption of synchronous reset is solved, and the metastable problem of asynchronous reset is also solved. The fundamental idea is also to synchronize asynchronous signals.

4G 3G MIFI

Wifi Router,Wireless Router,Mifi Device,LTE Hotspot

Shenhzhen Tongheng Weichuang Technology Co., Ltd , https://www.thwclte.com